For decades, lock-free programming has been the go-to optimization for the most contended parts of concurrent programs. The reasoning was simple: locks are slow under contention, so eliminate the locks. This made sense on the hardware of the time, and I should know—I've given several talks explaining how and why to do it.
The hardware has changed. Modern CPUs are very, very good at locks. Specifically, they are highly optimized for the operations that make locks fast: cache line transfers, memory ordering, and speculative execution through lock acquisitions. So good, in fact, that the old advice requires a serious reckoning.
In this talk, I will present extensive benchmarks across multiple CPU architectures—Intel, AMD, ARM server, and Apple silicon—that challenge the conventional wisdom about lock-free performance. We will see that under high contention, a well-implemented spinlock consistently outperforms lock-free atomics and CAS loops, often by massive margins. The reason is counterintuitive: lock-free operations under heavy contention flood the memory subsystem with coherence traffic, degrading not just the contending threads but the entire system. A spinlock serializes access cleanly and lets the rest of the machine get on with useful work.
To be clear: if your system strictly requires progress guarantees—such as avoiding deadlocks, priority inversion, or executing safely in a signal handler—lock-free techniques remain your only tool. But if you are reaching for lock-free data structures purely for throughput, the plot has completely flipped.
Lock-free programming is not dead; it has simply relocated. The same benchmarks show that for low-contention shared data—the occasional update, the lightly touched counter, the publishing protocol—atomics win decisively. There is no lock overhead, no pipeline disruption, just one fast instruction on the happy path.
We will also look at why these tradeoffs play out so differently on modern silicon: why AMD's streaming architecture pays a heavier price for lock disruption, why Apple silicon penalizes contended atomics more brutally than anyone else, and why "ARM vs x86" is the wrong way to think about it (what matters is the chip's market, not its instruction set).
If you've ever reached for a complex lock-free algorithm to speed up a highly contended hot path, this talk will change your mind about where lock-free programming truly belongs.
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Fedor G. Pikus is a Technical Fellow and the Director of the Advanced Projects Team at Siemens Digital Industries Software. His responsibilities include planning the long-term technical direction of Calibre products, directing and training the engineering teams, overseeing the design and architecture of the software, and researching new design and software technologies.
His earlier positions included Chief Scientist at Mentor Graphics (acquired by Siemens Software), Senior Software Engineer at Google, and Chief Software Architect for Calibre PERC, LVS, and DFM. He joined Mentor Graphics in 1998, making the switch from academic research in computational physics to the software industry.
Fedor is a recognized expert in high-performance computing and C++. He is an O'Reilly author and has written three books on C++ and software design. He is a regular instructor at the CppCon Academy, leading two of the best-attended classes, and has presented his work at CppNow, CppCon, CppNorth, SD West, DesignCon, and in various software development journals. Fedor holds over 30 patents and has authored over 100 papers and conference presentations on physics, EDA, software design, and the C++ language.